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| TECHNICAL DATA IN472-3 Liquid Crystal Display Controller The IN472-3-3 Liquid Crystal Display (LDC) Controller is a perpheral member of the COPSTM family, fabricated using CMOS technology. The IN472-3 drives a multiplexed liquid crystal directly. Data is loaded serially and is held in internal latches. The IN472-3 contains an on-chip oscillator and generates all the multi-level waveforms for back-planes and segment outputs on a triplex display. One IN472-3 can drive 36 segments multiplexed as 3 x 12 (41/2 digit display). Two IN472-3 devices can be used together to drive 72 segments (3 x 24) which could be an 81/2 digit display. * * * * * * * * * * * Direct interface to TRIPLEX LCD Low power dissipation (100 W typ.) Low cost Compatible with all COP400 processors Needs no refresh from processor On-chip oscillator and latches Expandable to longer displays Software compatible with COP470 V.F.Display Driver Chip Operates from display voltage MICROWIRETM compatible serial I/O 20-pin Dual-In-Line package ORDERING INFORMATION IN472-3N Plastic IN472-3DW SOIC TA = 0 to 70 C for all packages PIN ASSIGNMENT Pin Description Pin CS VDD GND DI SK BPA BPB BPC SA1SA4 Chip select Power supply (display voltage) Ground Serial data input Serial clock input Display backplane A (or oscillator in) Display backplane B Display backplane C (or oscillator out) 12 multiplexed outputs Description 1 IN472-3 DC ELECTRICAL CHARACTERISTICS (GND=0 V, VDD=3.0 V to 5.5 V, TA= 0C to 70C (depends on display characteristics) Guaranteed Limit Symbol VDD IDD VIL VIH VIL VIH VOL VOH VBPA,BPB,BPC ON VBPA,BPB,BPC OFF VBPA,BPB,BPC ON VBPA,BPB,BPC OFF VSEG ON VSEG OFF VSEG ON VSEG OFF Internal Oscillator Frequency Frame Time (Int. Osc. / 192) 1/TSCAN Scan Frequency SK Clock Frequency SK Width tSETUP tHOLD tSETUP tHOLD Output Loading Capacitance Note 2: V - 0.05VDD. DI Data Stup DI Data Hold CS Segment Outputs (SA1 SA4) Segment Outputs (SA1 SA4) Backplane Outputs (BPA,BPB,BPC) During BP - Time During BP + Time During BP - Time 0 2/3VDD -V 0 2/3VDD -V VDD -V 1/3VDD -V 15 2.4 39 4 1.7 1.0 100 1.0 1.0 100 pF V 2/3VDD +V V 2/3VDD +V VDD 1/3VDD +V 80 12.8 208 250 kHz ms Hz kHz s s ns s V V Backplane Outputs (BPA,BPB,BPC) During BP + Time VDD -V 1/3VDD -V VDD 1/3VDD +V V Output Levels, BPC (as Osc. Out) VDD-0.4 BPA (as Osc. in) VDD-0.6 Parameter Power Supply Voltage Power Supply Current (Note 1) Input Levels DI, SK, CS 0.7 VDD VDD =5.5 V Test Conditions Min 3.0 Max 5.5 250 0.8 VDD 0.6 VDD 0.4 VDD V V V Unit V A V Note 1: Power supply current as measured in stand-alone mode with all outputs open and all inputs at VDD. 2 IN472-3 Figure 1. Serial Load Timing Diagram Figure 2. Backplane and Segment Waveforms 3 |
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